1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device having a trench structure.
2. Description of Related Art
Conventionally, there are known trench gate type (trench structure) MOSFETs (metal oxide semiconductor field effect transistor) having a gate electrode embedded in a trench formed in a semiconductor layer. For these trench gate type MOSFETs (semiconductor devices), as a material to form the gate electrodes, polysilicon made conductive by being doped with an impurity is generally used.
On the other hand, in these days, by reducing the resistance of a gate electrode, speeding up of the switching operation of a MOSFET is attempted. In the above-described MOSFETs having a gate electrode made of polysilicon, by increasing the amount of impurity with which polysilicon is doped (doping concentration), it is possible to reduce the resistance of the gate electrode. However, there is a limit to the solid solubility of an impurity in polysilicon, and therefore, in order to further reduce the resistance of the gate electrode, it is necessary to form the gate electrode from a metal material with a specific resistance (electrical resistivity) lower than that of polysilicon.
For this reason, conventionally, there are known trench gate type MOSFETs with a gate electrode made of a metal material. Such MOSFETs are, for example, disclosed in Japanese Unexamined Patent Application No. 2001-284587. Japanese Unexamined Patent Application No. 2001-284587 just mentioned discloses a MOSFET (semiconductor device) having a gate electrode, made of tungsten, formed inside a trench.
FIG. 22 is a sectional view showing the conventional MOSFET (semiconductor device) disclosed in Japanese Unexamined Patent Application No. 2001-284587 mentioned above with its structure simplified. With reference to FIG. 22, in the conventional MOSFET (semiconductor device), an epitaxial layer (semiconductor layer) 102 is formed on the upper surface of an n+-type semiconductor substrate 101. In the epitaxial layer 102, in the order from the semiconductor substrate 101 side, there are formed an n−-type doped region (drain region) 102a, a p-type doped region 102b, and an n+-type doped region (source region) 102c. 
In the epitaxial layer 102, there is also formed a trench 103 which penetrates through the n+-type doped region (source region) 102c, through the p-type doped region 102b, and halfway through the n.sup.-type doped region (drain region) 102a. At the floor and interior side surfaces of the trench 103, there is formed a gate insulating film 104 made of SiO2. On the gate insulating film 104 inside the trench 103, there is formed, with a SiN film 105 interposed, a gate electrode 106 made of tungsten. The SiN film 105 is formed, with the gate insulating film 104 interposed, on the entire surface inside the trench 103 (on the floor and interior side surfaces of the trench 103). On the upper surface of the epitaxial layer 102, there is formed an UDO (undoped oxide) film 107 which covers the upper and sides surfaces of the gate electrode 106, and on the UDO film 107, there is formed a source electrode 108. On the reverse surface (lower surface) of the semiconductor substrate 101, a drain electrode 109 is formed. Note that the source electrode 108 and the n+-type doped region (source region) 102care electrically connected together via unillustrated contact electrodes.
In the conventional MOSFET structured as described above, by applying a predetermined voltage between the source electrode 108 and the drain electrode 109, and in addition setting the gate electrode 106 to a predetermined potential, a channel region 110 is formed in a region in the vicinity of the interface between the p-type doped region 102b and the gate insulating film 104 (a region in the p-type doped region 102b along the trench 103-side wall). Thus, a current flows between the n+-type doped region (source region) 102c and the n−-type doped region (drain region) 102a. Note that the gate electrode 106 and the SiN film 105 face the channel region 110.
In the conventional MOSFET described above, since the gate electrode 106 made of tungsten is formed with the SiN film 105 interposed, with the SiN film 105, diffusion of metal atoms (tungsten atoms) into the gate insulating film 104 is reduced.
In the conventional MOSFET shown in FIG. 22, however, it is necessary to form the SiN film 105 on the entire surface inside the trench 103, and this leads to a problem of difficulty in forming the SiN film 105. In these days, trench patterns are becoming increasingly fine, and even trenches with depths about 1 μm to 3 μm and width about 0.3 μm to 0.5 μm are formed. In a case where a trench having such a large aspect ratio is formed in the conventional MOSFET described above, formation of the SiN film 105 is extremely difficult. This may lead to a problem that part of the inside of the trench 103 remains uncovered with the SiN film 105, and in this case, via this part, metal atoms of the gate electrode 106 may inconveniently diffuse into the gate insulating film 104. Thus, the reliability of the gate insulating film 104 is lowered.
It is also difficult to embed, with a satisfactory result, tungsten (a metallic material, namely the gate electrode 106) inside the trench having a large aspect ratio. With the conventional MOSFET shown in FIG. 22, it is therefore difficult to cope with a finer trench pattern.
Furthermore, in the conventional structure shown in FIG. 22, because the gate electrode 106 is made of tungsten, compared with a case where the gate electrode is made of polysilicon, the driving voltage of the MOSFET inconveniently varies greatly.
Here, the driving voltage of a MOSFET is given by
Threshold value
                              V          T                =                ⁢                              V            FB                    +                      2            ⁢                                                  ⁢                          ψ              B                                +                                                    (                                  2                  ⁢                                                                          ⁢                                      ɛ                    S                                    ⁢                                                            qN                      A                                        ⁡                                          (                                              2                        ⁢                                                  ψ                          B                                                                    )                                                                      )                                            1                /                2                                      /                          C              O                                                              =                ⁢                              (                          φ              -                                                Q                  f                                /                                  C                  O                                                      )                    +                      2            ⁢                                                  ⁢                          ψ              B                                +                                                    (                                  4                  ⁢                                                                          ⁢                                      ɛ                    S                                    ⁢                                      qN                    A                                    ⁢                                      ψ                    B                                                  )                                            1                /                2                                      /                          C              O                                          where VFB is the flat band voltage, φB is the internal electrostatic potential of the semiconductor (p-type doped region 102b), εs is the dielectric constant of the semiconductor (p-type doped region 102b), q is the amount of electric charge of an electron, NA is the concentration of the acceptor impurity, CO is the capacity per unit area of the gate insulating film 104, φ is the difference in work function (the difference between the work functions of the gate electrode 106 and the semiconductor (p-type doped region 102b) facing each other with the gate insulating film 104 lying in between), and Qf is the fixed charge within the gate insulating film 104.
In a case where the gate electrode 106 is made of tungsten, compared with a case where the gate electrode is made of polysilicon, since the difference in work function φ greatly varies, according to the above-described formula, in the conventional MOSFET shown in FIG. 22, compared with common MOSFETs where the gate electrode is made of polysilicon, the threshold value VT greatly varies. Thus, inconveniently, as described above, the driving voltage varies greatly.
In the conventional structure described above, because the gate electrode 106 made of tungsten is formed so as to face the channel region 110 with the gate insulating film 104 and the SiN film 105 interposed, due to the thickness of the SiN film 105, the difference in dielectric constant between the gate insulating film 104 and the SiN film 105, and for other causes, the device characteristics such as the driving voltage may inconveniently vary.
As described above, with the conventional MOSFET shown in FIG. 22, although it is possible to reduce the resistance of the gate electrode 106, the device characteristics such as the driving voltage may inconveniently vary greatly. To avoid variations in the device characteristics such as the driving voltage, a major design change is required in the MOSFET. That is, with the conventional MOSFET shown in FIG. 22, it is difficult to speed up the switching operation, while reducing variations in the device characteristics such as the driving voltage.